In the related art, there is a technique of storing multiple types of arrival packets in a plurality of reception buffers for each type and reading out a packets from the plurality of reception buffers according to predetermined priority control content.
For example, in packet-based transaction, an ordering rule of packet forwarding based on a priority assigned to each packet is applied so as not to cause deadlock due to the stall of transaction. In the case of forwarding packets according to the order determined based on this rule, for example, a plurality of reception buffers provided for each packet type and a mechanism to hold/refer to the packet arrival order are prepared. The packet arrival order is prepared to forward the packets in the packet arrival order. Meanwhile, the plurality of reception buffers are prepared for inter-packet pass forwarding according to the priority. The inter-packet pass forwarding represents to forward a packet having a certain type before a packet which has another type and has been reached earlier than the packet having the certain type, according to the priority.
FIG. 9 illustrates a packet read-out control apparatus which is one of conventional techniques. The packet read-out control apparatus illustrated in FIG. 9 generates and records tags as order information indicating the arrival order for each packet, in order to hold and refer to the order information of arrival packets.
To be more specific, in the packet read-out control apparatus illustrated in FIG. 9, when reception packets reach, according to the type identifiers in the reception packets, the reception packets are respectively stored in one of a plurality of reception buffers (FIFO: First In First Out) prepared for each packet type (“A”, “B” and “C” in this case).
Meanwhile, when reception packets reach, a reception trigger is generated and the type identifiers in the reception packets are input in a tag generation circuit. In the tag generation circuit, in the wake of the reception trigger, a reception order tag generation counter generates reception order tags corresponding to the type identifiers. The reception order tags are respectively stored in one of a plurality of tag buffers (FIFO) prepared for each packet type, according to the type identifiers.
An arbitration circuit reads out a tag value stored in the head of each of the plurality of tag buffers, refers to the reception order indicating each tag value, and checks the reception order (arrival order) of the packet corresponding to each tag value, namely the packet stored in the head of each reception buffer. Meanwhile, the arbitration circuit determines a packet to be read out, according to predetermined priority control content, namely an ordering rule (read-out rule) between packet types, and provides a read-out instruction to a reception buffer. Thus, the packet is read out from the corresponding reception buffer and forwarded.    Patent Document 1: Japanese National Publication of International Patent Application No. 2005-518578    Patent Document 2: Japanese Laid-Open Patent Publication No. 2-117241    Patent Document 3: Japanese Laid-Open Patent Publication No. 5-227210    Patent Document 4: Japanese Laid-Open Patent Publication No. 11-298521
However, the above conventional technique has the following problem. That is, if a tag indicating the order of each packet is generated and recorded in a tag buffer, the circuit amount of the tag buffer itself increases. For example, it is presumed that there are three reception buffers and each of these reception buffers can store 16 packets. Meanwhile, in a case where each reception buffer stores 16 packets of the maximum storage number, when the tag value generated for each packet indicates the arrival order of each packet, it is requested that the tag values represent the sum of the maximum storage numbers of the reception buffers, that is, values of 48 (16×3=48) patterns. In this case, the minimum bit number to indicate the tag values of 48 patterns is six bits.
Therefore, the minimum capacity for the tag buffers is 288 bits (6 (tag value)×16 (packet maximum storage number)×3 (reception buffer number)=288 [bit]).